//<<< Use Configuration Wizard in Context Menu >>>

#ifndef __Visual_Configuration_Management_H
#define __Visual_Configuration_Management_H
#include "csa37f7x_afe.h"
 
//文件作用：
//1、统一可视化配置全局项目相关的宏定义
//2、语法链接：https://blog.csdn.net/wo0007/article/details/85288481
//////////////////////////////////////////////////////////////////////////////////////////
/***************************项目设置********************************/
//<h>set project id
//<o>PROJECT_ID  
//<i>project id
#define PROJECT_ID			        208
//</h>
/***********************************************************/
/***************************固件版本设置********************************/
//<h>set code main & sub version
//<o>MAIN_VER  
//<i>main version : 00~99
#define MAIN_VER	                100

//<o>SUB_VER
//<i>sub version : 00~99
#define SUB_VER	                    10
//</h>
/***********************************************************/
/***************************硬件相关设置********************************/
//<h>Define For NDT Sensors
//<o>CH_G1
//<i>set CH_G1 num
#define CH_G1	                        1
//<o>MODEL_G1
//<i>set MODEL_G1 num
#define MODEL_G1	                    0
//<o>BU_G1
//<i>set BU_G1 num
#define BU_G1	                        1
//<o>MODEL_DF_G1
//<i>set MODEL_DF_G1 num
#define MODEL_DF_G1	                    0

//<o>CH_G2
//<i>set CH_G2 num
#define CH_G2	                        1
//<o>MODEL_G2
//<i>set MODEL_G2 num
#define MODEL_G2	                    0
//<o>BU_G2
//<i>set BU_G2 num
#define BU_G2	                        1
//<o>MODEL_DF_G2
//<i>set MODEL_DF_G2 num
#define MODEL_DF_G2	                    0

//<o>GR_COUNT
//<i>set GR_COUNT num
#define GR_COUNT	                        2
//<o>SA_COUNT
//<i>set SA_COUNT num
#define SA_COUNT	                    1
//<o>PHY_CH_COUNT
//<i>set PHY_CH_COUNT num
#define PHY_CH_COUNT	                    2

//<o>GP_IN_COUNT
//<i>GP_IN_COUNT
#define GP_IN_COUNT		0
//<o>GP_OUT_COUNT
//<i>set GP_OUT_COUNT num
#define GP_OUT_COUNT	4
#define GP_COUNT        (GP_IN_COUNT + GP_OUT_COUNT)

#define CH_COUNT		(CH_G1 + CH_G2)
#define BU_COUNT		(BU_G1 + BU_G2)
//</h>
/***********************************************************/
/***************************算法相关设置********************************/
// <h> Configuration NDT Algorithm option
//<o>SAMPLE_COUNT  
//<i>SAMPLE_COUNT
#define SAMPLE_COUNT			        50
//<o>AVG_POWER_COUNT  
//<i>AVG_POWER_COUNT
#define AVG_POWER_COUNT			        6
//<o>BASE_LINE_NARROW  
//<i>BASE_LINE_NARROW
#define BASE_LINE_NARROW			    100
//<o>BASE_LINE_WIDTH  
//<i>BASE_LINE_WIDTH
#define BASE_LINE_WIDTH			        800
/***********************/
// <h> force flag option
// <o> FF_TRI_TH
// <i> FF_TRI_TH
#define FF_TRI_TH					(20)
// <o> FF_REL_TH
// <i> FF_REL_TH
#define FF_REL_TH       (15)
// <o> FF_LOCAL_TH
// <i> FF_LOCAL_TH
#define FF_LOCAL_TH     (FF_TRI_TH - 10)
// <o> FF_SLP_TH1
// <i> FF_SLP_TH1
#define FF_SLP_TH1	    (2)	   // force flag slp threshold
// <o> FF_SLP_TH2
// <i> FF_SLP_TH2
#define FF_SLP_TH2	    (0)	   // force flag slp threshold
// <o> FF_LEAVE_COEF
// <i> FF_LEAVE_COEF
#define FF_LEAVE_COEF	(0.2)
// </h>
 
/***********************/
// <h> baseline option
// <o> BASELINE_SALPHA
// <i> BASELINE_SALPHA
#define BASELINE_SALPHA					(10)	//0.1*1024
// <o> BASE_CHANGE_LIMIT
// <i> BASE_CHANGE_LIMIT
#define BASE_CHANGE_LIMIT        (1 << 8)
// <o> ORDER16_BASE
// <i> ORDER16_BASE
#define ORDER16_BASE     (4)
// <o> ORDER16
// <i> ORDER16
#define ORDER16	    (1 << ORDER16_BASE)

// </h>
/***********************/
// </h>
/***********************/
//<h>set sacn period
//<o>DF_HIGH_SPEED  
//<i>DF_HIGH_SPEED
#define DF_HIGH_SPEED			        6
//<o>DF_LOW_SPEED  
//<i>DF_LOW_SPEED
#define DF_LOW_SPEED			        100
//<o>DF_POWER_OFF  
//<i>DF_POWER_OFF
#define DF_POWER_OFF			        1000
//</h>


/***********************************************************/
//<h>adc bit
//<o>ADC_ACCURACY_12BIT
//<i>Selection of A/D data bit
// <0=> 24bit 
// <1=> 12bit 
#define ADC_ACCURACY_12BIT	                            1
//</h>
/***************************AFE设置********************************/
//<h>set AFE ref
// <q> AFE_INT_EN
// <i> enable/diasble AFE interrupt
#define AFE_INT_EN										1
// <q> AFE_PGA_EN
// <i> enable/diasble PGA function
#define AFE_PGA_EN										1
 
//<o>AFE_GAIN1  
//<i>AFE_GAIN1:1/16/32/64/128/256
// <2=>  AFE_PGA_1_GAIN_2    
// <16=>  AFE_PGA_1_GAIN_16 
// <32=>  AFE_PGA_1_GAIN_32  
// <64=>  AFE_PGA_1_GAIN_64  
// <128=>  AFE_PGA_1_GAIN_128  
#define AFE_GAIN1			                            64
#if (AFE_GAIN1==2)
#define AFE_PGA1_GAIN	   AFE_PGA_1_GAIN_2
#elif (AFE_GAIN1==16)
#define AFE_PGA1_GAIN	   AFE_PGA_1_GAIN_16
#elif (AFE_GAIN1==32)
#define AFE_PGA1_GAIN	   AFE_PGA_1_GAIN_32
#elif (AFE_GAIN1==64)
#define AFE_PGA1_GAIN	   AFE_PGA_1_GAIN_64
#elif (AFE_GAIN1==128)
#define AFE_PGA1_GAIN	   AFE_PGA_1_GAIN_128
#endif

//<o>AFE_GAIN2  
//<i>AFE_GAIN2:1/8
// <1=>  AFE_PGA_2_GAIN_1    
// <8=>  AFE_PGA_2_GAIN_8
#define AFE_GAIN2			                            8
#if (AFE_GAIN2==1)
#define AFE_PGA2_GAIN	   AFE_PGA_2_GAIN_1
#elif (AFE_GAIN2==8)
#define AFE_PGA2_GAIN	   AFE_PGA_2_GAIN_8
#endif

//<o>AFE_AVG_MODE_
//<i>Selection of A/D data preprocessing mode in period-limited scan mode
// <0=> average 
// <1=> average_wihtoutMAXMIN 
#define AFE_AVG_MODE_	                                1
#if (AFE_AVG_MODE_==0)
#define AFE_AVG_MODE	   CAL_S_0
#elif (AFE_AVG_MODE_==1)
#define AFE_AVG_MODE	   CAL_S_1
#endif

//<o>AFE_ADC_SAMPLE_CLK_
//<i>ADC Valid period conversion times the sampling count multiplied by the ADC clock period
// <0=>  ADC_SAMPLE_CLK_17    
// <1=>  ADC_SAMPLE_CLK_33 
// <2=>  ADC_SAMPLE_CLK_65  
// <3=>  ADC_SAMPLE_CLK_129  
// <4=>  ADC_SAMPLE_CLK_257  
// <5=>  ADC_SAMPLE_CLK_513  
// <6=>  ADC_SAMPLE_CLK_1025  
// <7=>  ADC_SAMPLE_CLK_2049  
#define AFE_ADC_SAMPLE_CLK_	                            1
#if (AFE_ADC_SAMPLE_CLK_==0)
#define AFE_ADC_SAMPLE_CLK	   ADC_SAMPLE_CLK_17
#elif (AFE_ADC_SAMPLE_CLK_==1)
#define AFE_ADC_SAMPLE_CLK	   ADC_SAMPLE_CLK_33
#elif (AFE_ADC_SAMPLE_CLK_==2)
#define AFE_ADC_SAMPLE_CLK	   ADC_SAMPLE_CLK_65
#elif (AFE_ADC_SAMPLE_CLK_==3)
#define AFE_ADC_SAMPLE_CLK	   ADC_SAMPLE_CLK_129
#elif (AFE_ADC_SAMPLE_CLK_==4)
#define AFE_ADC_SAMPLE_CLK	   ADC_SAMPLE_CLK_257
#elif (AFE_ADC_SAMPLE_CLK_==5) 
#define AFE_ADC_SAMPLE_CLK	   ADC_SAMPLE_CLK_513
#elif (AFE_ADC_SAMPLE_CLK_==6)
#define AFE_ADC_SAMPLE_CLK	   ADC_SAMPLE_CLK_1025
#elif (AFE_ADC_SAMPLE_CLK_==7)
#define AFE_ADC_SAMPLE_CLK	   ADC_SAMPLE_CLK_2049
#endif

//<o>AFE_CYCLE_MODE_VALID_NUM_
//<i>ADC Number of valid period conversions
// <0=>  ADC_CONVER_VALID_NUM_2    
// <1=>  ADC_CONVER_VALID_NUM_4 
// <2=>  ADC_CONVER_VALID_NUM_8  
// <3=>  ADC_CONVER_VALID_NUM_16  
// <4=>  ADC_CONVER_VALID_NUM_32  
// <5=>  ADC_CONVER_VALID_NUM_64  
// <6=>  ADC_CONVER_VALID_NUM_128  
// <7=>  ADC_CONVER_VALID_NUM_256  
#define AFE_CYCLE_MODE_VALID_NUM_	                    3
#if (AFE_CYCLE_MODE_VALID_NUM_==0)
#define AFE_CYCLE_MODE_VALID_NUM	   ADC_CONVER_VALID_NUM_2
#elif (AFE_CYCLE_MODE_VALID_NUM_==1)
#define AFE_CYCLE_MODE_VALID_NUM	   ADC_CONVER_VALID_NUM_4
#elif (AFE_CYCLE_MODE_VALID_NUM_==2)
#define AFE_CYCLE_MODE_VALID_NUM	   ADC_CONVER_VALID_NUM_8
#elif (AFE_CYCLE_MODE_VALID_NUM_==3)
#define AFE_CYCLE_MODE_VALID_NUM	   ADC_CONVER_VALID_NUM_16
#elif (AFE_CYCLE_MODE_VALID_NUM_==4)
#define AFE_CYCLE_MODE_VALID_NUM	   ADC_CONVER_VALID_NUM_32
#elif (AFE_CYCLE_MODE_VALID_NUM_==5)
#define AFE_CYCLE_MODE_VALID_NUM	   ADC_CONVER_VALID_NUM_64
#elif (AFE_CYCLE_MODE_VALID_NUM_==6)
#define AFE_CYCLE_MODE_VALID_NUM	   ADC_CONVER_VALID_NUM_128
#elif (AFE_CYCLE_MODE_VALID_NUM_==7)
#define AFE_CYCLE_MODE_VALID_NUM	   ADC_CONVER_VALID_NUM_256
#endif

//<o>AFE_ADC_CHSU_
//<i>ADC Channel establishment time selection
// <0=>  10us  
// <1=>  20us
// <2=>  30us
// <3=>  40us 
#define AFE_ADC_CHSU_	                                1
#if (AFE_ADC_CHSU_==0)
#define AFE_ADC_CHSU	   CHSU_10
#elif (AFE_ADC_CHSU_==1)
#define AFE_ADC_CHSU	   CHSU_20
#elif (AFE_ADC_CHSU_==2)
#define AFE_ADC_CHSU	   CHSU_40
#elif (AFE_ADC_CHSU_==3)
#define AFE_ADC_CHSU	   CHSU_80
#endif

//<o>AFE_ADC_SAMPLE_CLK_IDLE_
//<i>ADC Valid period conversion times the sampling count multiplied by the ADC clock period
// <0=>  ADC_SAMPLE_CLK_17    
// <1=>  ADC_SAMPLE_CLK_33 
// <2=>  ADC_SAMPLE_CLK_65  
// <3=>  ADC_SAMPLE_CLK_129  
// <4=>  ADC_SAMPLE_CLK_257  
// <5=>  ADC_SAMPLE_CLK_513  
// <6=>  ADC_SAMPLE_CLK_1025  
// <7=>  ADC_SAMPLE_CLK_2049  
#define AFE_ADC_SAMPLE_CLK_IDLE_	                            0
#if (AFE_ADC_SAMPLE_CLK_IDLE_==0)
#define AFE_ADC_SAMPLE_CLK_IDLE	   ADC_SAMPLE_CLK_17
#elif (AFE_ADC_SAMPLE_CLK_IDLE_==1)
#define AFE_ADC_SAMPLE_CLK_IDLE	   ADC_SAMPLE_CLK_33
#elif (AFE_ADC_SAMPLE_CLK_IDLE_==2)
#define AFE_ADC_SAMPLE_CLK_IDLE	   ADC_SAMPLE_CLK_65
#elif (AFE_ADC_SAMPLE_CLK_IDLE_==3)
#define AFE_ADC_SAMPLE_CLK_IDLE	   ADC_SAMPLE_CLK_129
#elif (AFE_ADC_SAMPLE_CLK_IDLE_==4)
#define AFE_ADC_SAMPLE_CLK_IDLE	   ADC_SAMPLE_CLK_257
#elif (AFE_ADC_SAMPLE_CLK_IDLE_==5) 
#define AFE_ADC_SAMPLE_CLK_IDLE	   ADC_SAMPLE_CLK_513
#elif (AFE_ADC_SAMPLE_CLK_IDLE_==6)
#define AFE_ADC_SAMPLE_CLK_IDLE	   ADC_SAMPLE_CLK_1025
#elif (AFE_ADC_SAMPLE_CLK_IDLE_==7)
#define AFE_ADC_SAMPLE_CLK_IDLE	   ADC_SAMPLE_CLK_2049
#endif

//<o>AFE_CYCLE_MODE_VALID_NUM_IDLE_
//<i>ADC Number of valid period conversions
// <0=>  ADC_CONVER_VALID_NUM_2    
// <1=>  ADC_CONVER_VALID_NUM_4 
// <2=>  ADC_CONVER_VALID_NUM_8  
// <3=>  ADC_CONVER_VALID_NUM_16  
// <4=>  ADC_CONVER_VALID_NUM_32  
// <5=>  ADC_CONVER_VALID_NUM_64  
// <6=>  ADC_CONVER_VALID_NUM_128  
// <7=>  ADC_CONVER_VALID_NUM_256  
#define AFE_CYCLE_MODE_VALID_NUM_IDLE_	                    1
#if (AFE_CYCLE_MODE_VALID_NUM_IDLE_==0)
#define AFE_CYCLE_MODE_VALID_NUM_IDLE	   ADC_CONVER_VALID_NUM_2
#elif (AFE_CYCLE_MODE_VALID_NUM_IDLE_==1)
#define AFE_CYCLE_MODE_VALID_NUM_IDLE	   ADC_CONVER_VALID_NUM_4
#elif (AFE_CYCLE_MODE_VALID_NUM_IDLE_==2)
#define AFE_CYCLE_MODE_VALID_NUM_IDLE	   ADC_CONVER_VALID_NUM_8
#elif (AFE_CYCLE_MODE_VALID_NUM_IDLE_==3)
#define AFE_CYCLE_MODE_VALID_NUM_IDLE	   ADC_CONVER_VALID_NUM_16
#elif (AFE_CYCLE_MODE_VALID_NUM_IDLE_==4)
#define AFE_CYCLE_MODE_VALID_NUM_IDLE	   ADC_CONVER_VALID_NUM_32
#elif (AFE_CYCLE_MODE_VALID_NUM_IDLE_==5)
#define AFE_CYCLE_MODE_VALID_NUM_IDLE	   ADC_CONVER_VALID_NUM_64
#elif (AFE_CYCLE_MODE_VALID_NUM_IDLE_==6)
#define AFE_CYCLE_MODE_VALID_NUM_IDLE	   ADC_CONVER_VALID_NUM_128
#elif (AFE_CYCLE_MODE_VALID_NUM_IDLE_==7)
#define AFE_CYCLE_MODE_VALID_NUM_IDLE	   ADC_CONVER_VALID_NUM_256
#endif

//<o>AFE_ADC_CHSU_IDLE_
//<i>ADC Channel establishment time selection
// <0=>  10us  
// <1=>  20us
// <2=>  30us
// <3=>  40us 
#define AFE_ADC_CHSU_IDLE_	                                0
#if (AFE_ADC_CHSU_IDLE_==0)
#define AFE_ADC_CHSU_IDLE	   CHSU_10
#elif (AFE_ADC_CHSU_IDLE_==1)
#define AFE_ADC_CHSU_IDLE	   CHSU_20
#elif (AFE_ADC_CHSU_IDLE_==2)
#define AFE_ADC_CHSU_IDLE	   CHSU_40
#elif (AFE_ADC_CHSU_IDLE_==3)
#define AFE_ADC_CHSU_IDLE	   CHSU_80
#endif

//<o>AFE_SCAN_MODE_
//<i>ADC Transform the operational mode definition
// <0=>  ADC_SINGLE_CONVER    
// <1=>  ADC_SINGLE_CYCLE_SACAN 
// <2=>  ADC_FINITE_PERIOD_SCAN_MODE_1  
// <3=>  ADC_BURST_MODE  
#define AFE_SCAN_MODE_	     2
#if (AFE_SCAN_MODE_==0)
#define AFE_SCAN_MODE	   ADC_SINGLE_CONVER
#elif (AFE_SCAN_MODE_==1)
#define AFE_SCAN_MODE	   ADC_SINGLE_CYCLE_SACAN
#elif (AFE_SCAN_MODE_==2)
#define AFE_SCAN_MODE	   ADC_FINITE_PERIOD_SCAN_MODE_1
#elif (AFE_SCAN_MODE_==3)
#define AFE_SCAN_MODE	   ADC_BURST_MODE
#endif

//<o>AFE_VS_SEL_
//<i>vs power
// <0=> 2.0V
// <1=> 2.2V
// <2=> 2.6V
// <3=> 2.8V
#define AFE_VS_SEL_	                3
#if (AFE_VS_SEL_==0)
#define AFE_VS_SEL	   VS20
#elif (AFE_VS_SEL_==1)
#define AFE_VS_SEL	   VS20
#elif (AFE_VS_SEL_==2)
#define AFE_VS_SEL	   VS26
#elif (AFE_VS_SEL_==3)
#define AFE_VS_SEL	   VS28
#endif
/***********************************************************/



#endif  /* __SYSTEM_CONTROL_H */
//<<< end of configuration section >>>

